1. Field of the Invention
The present invention relates to a method of fabricating semiconductor devices. More particularly, the present invention relates to a photolithographic process of fabricating a photoresist pattern, and to the quality control of such a process.
2. Description of the Related Art
Semiconductor devices are dramatically evolving in conjunction with rapid developments in the fields of data communications and data processing. In these fields, especially, semiconductor devices must operate at high speeds and at the same time to have a large storage capacity. In response to these requirements, techniques of fabricating semiconductor devices are being studied and developed with the aim of maximizing the integration, reliability, response speed, etc., of the devices.
The fabricating of semiconductor devices typically includes a deposition process of forming a target film on a semiconductor substrate, a photolithography process of forming and patterning a photoresist layer on the target film, an etching process of selectively removing the portions of the target film exposed by the photoresist pattern, and a cleaning process of removing the photoresist pattern and the residue resulting from the etching process using a cleaning solution so that only the portion of the target film which was not removed by the etching process is left. The photolithography process entails directing exposure light onto the photoresist layer through a mask or reticle (hereinafter “photomask”) having a pattern that is thereby transcribed onto the photoresist layer, and developing the exposed photoresist layer. As a result, selective portions of the photoresist layer are removed and the remaining portions constitute the photoresist pattern. The critical dimension of the photoresist pattern is dependent upon the energy level of the exposure light emitted onto the photoresist layer through the photomask.
However, as semiconductor devices become more highly integrated, the design rules of the devices become smaller and smaller, i.e., patterns having very small critical dimensions (CD) must be formed. These patterns often include a series of contact holes or a series of lines and spaces. Several techniques have been suggested for improving the photolithography process so that a fine pattern can be formed, e.g., a pattern comprising contact holes having small diameters or a pattern comprising lines and spaces having small widths.
Known photolithographic techniques for forming fine contact holes include the use of an E-beam having a short wavelength to expose the photoresist, and the use of a half-tone phase shift mask as the photomask. Of these techniques, the use of exposure light having a short wavelength poses a number of difficulties in terms of its dependence on photoresist having certain compositions and in terms of its high cost. The use of a half-tone phase shift mask is problematic in that it is difficult to fabricate such a mask in the first place. Also, it is actually difficult to form lines or contact holes having a CD less than 150 nm using a half-tone phase shift mask because of the phenomena of interference or diffraction that occurs during the exposure process.
Furthermore, another conventional technique comprises reflowing the photoresist pattern to thereby reduce the size of openings in the photoresist pattern (used for forming contact holes in the target layer) or to reduce the width of the spaces in photoresist pattern (used for forming lines in the target layer). In this technique, a photoresist film is formed on a wafer, the film Is patterned by a lithography process, and the resultant photoresist pattern is heated to a temperature higher than a so-called glass transfer temperature or the temperature at which the photoresist softens. As a result, the photoresist begins to reflow such that the critical dimension (CD) of the photoresist pattern is reduced.
A method of fabricating such a photoresist pattern is disclosed in U.S. Pat. No. 6,444,410, and the composition of a photoresist used for the fabrication of such a photoresist pattern is disclosed in U.S. Pat. No. 6,485,895.
Hereinafter, a prior art method of fabricating a photoresist pattern will be described with reference to the flowchart of FIG. 1. As shown in FIG. 1, a target layer, in which a main pattern is to be formed (such as a pattern of lines or contact holes), is first coated with photoresist (S101). The target layer may be a semiconductor substrate or a layer of material formed on the semiconductor substrate. The substrate is also subjected to a first annealing (i.e., a soft bake) so that a solvent component of the photoresist is removed from the photoresist layer formed on the substrate (S102).
The photoresist is then exposed to light of a certain wavelength via a photomask bearing a pattern corresponding to the main pattern (S103). Following the exposure process, a second annealing (i.e., a post exposure bake) is performed to minimize the amount of solvent remaining in the photoresist (S104).
The semiconductor substrate having the photoresist film formed thereon is then immersed in a developer solution. At this time, either the exposed portion of the photoresist is removed by the developer solution (positive type of photoresist) or the non-exposed portion is removed by the developer solution (negative type of photoresist) (S105). Accordingly, the photoresist is patterned. The photoresist pattern will serve as an etch mask for the formation of lines or contact holes in a portion of the underlying (target) layer located in a device-forming region of the semiconductor substrate. In the case of forming devices, such as transistors, the lines will electrically connect the devices, and the contact holes will extend through an interlayer insulating film formed on the semiconductor substrate to electrically connect devices or lines on opposite sides of the interlayer insulating film. The resultant product may be cleaned at this time.
Subsequently, the photoresist pattern is subjected to a third annealing (i.e., a hard bake) so that the photoresist pattern is stabilized after the developing or cleaning process (S106). Note, the first to third annealings are performed at the glass transfer temperature of the photoresist to evaporate the solvent contained in the photoresist and solidify the photoresist layer.
At this time, the critical dimension (CD) of the openings (holes or spaces) of the photoresist pattern is no smaller than the wavelength of the light that was used to expose the photoresist. Therefore, a fourth annealing (a photoresist reflow process) is performed for a predetermined time at a temperature higher than the glass transfer temperature of the photoresist to improve the profile of the photoresist pattern and to reduce the critical dimension (CD) of the openings of photoresist pattern (S107).
Furthermore, an after develop inspection (ADI) is conducted to confirm whether the critical dimension of the photoresist pattern, which is established after the third annealing, is within certain design parameters. Also, an after flow inspection (AFI) is conducted (S108) to confirm whether the reduced critical dimension, i.e., the critical dimension of the openings of the photoresist pattern after the fourth annealing, is within certain design parameters. The ADI and AFI are conducted using scanning electron spectroscopy. For reasons of productivity and economics, the after develop inspection of products is performed only if the after flow inspection uncovers a defect in a photoresist pattern.
More specifically, a number of semiconductor substrates received in a cassette, namely, one lot of substrates, are processed at a time by photolithography equipment, semiconductor fabrication equipment, and the like. For example, when a semiconductor device having transistors comprising a plurality of gate stacks are to be fabricated, contact holes must be formed in an interlayer insulating film of the device to expose the source/drain electrodes of the transistors. In this case, twenty-five semiconductor substrates are loaded in a cassette and the twenty-five semiconductor substrates are then subjected in sequence to a photolithography process to form photoresist patterns, on the substrates, respectively. The photoresist patterns correspond to the pattern of contact holes to be formed in the interlayer insulating film. Subsequently, i.e., when the photolithography process is completed with respect to the twenty-five semiconductor substrates, the cassette containing the twenty-five semiconductor substrates is transported to etching equipment. In the etching equipment, each of the semiconductor substrates is subjected to an etching process using the photoresist pattern as an etching mask. At this time, one semiconductor substrate is randomly selected from the lot, and is subjected to the after flow inspection. The after flow inspection is used to determine whether the photolithography process performed on the lot is defective (SI 08).
If the after flow inspection reveals that the photolithography process performed on the relevant lot is defective, a test process 11 is carried out. The test process 11 corresponds to the original fabrication process up through the third annealing. The test process 11 is for producing a substrate that will be subjected to an after develop inspection.
The test process II will be described in detail. If any lot does not pass the after flow inspection, a semiconductor substrate is selected from the lot after the lot is cleaned or a semiconductor substrate is selected from another lot which has not yet been subjected to the photolithography process. The selected substrate is subsequently coated with the photoresist (S111). Then, the photoresist formed on the semiconductor substrate is subjected to a first annealing so that solvent contained in the photoresist is removed (S112). Subsequently, the photoresist is selectively exposed to light of a certain wavelength through a photomask bearing an image of the main pattern (S113). After the exposure process is performed, a second annealing (i.e., a post expose bake) is performed to further reduce the amount of solvent in the photoresist (S114).
The semiconductor substrate having the photoresist formed thereon is immersed and developed in a developer solution (S115), whereby the layer of photoresist is patterned. The photoresist pattern is subjected to a third annealing (i.e., a hard bake) so that the photoresist pattern is solidified and stabilized (S116). Finally, the photoresist pattern formed on the semiconductor substrate is inspected (S117). If the photoresist pattern has a critical dimension that matches that of the pattern borne by the photomask used in the exposure process, the application temperature or time of the fourth annealing is regarded as being improper. At this time, the process temperature or time of the fourth annealing is tested, modified, and then applied in the mass-production process. On the other hand, if the critical dimension of the photoresist pattern does not match that of the photomask, the after develop inspection confirms that the process defect occurs prior to the fourth annealing. The exact cause of the process defect is then uncovered. To this end, the exposure process and the first to third annealing processes are sequentially inspected one by one.
Thus, the method of fabricating a photoresist pattern according to the prior art makes it is possible to recognize whether defects are associated with the fourth annealing. However, the method of fabricating the photoresist pattern according to the prior art presents the following problems.
First, if the after flow inspection reveals that the process defect is associated with the photolithography process, the after develop inspection is conducted on a semiconductor substrate selected from a lot which has not yet been subjected to the photolithography process, or the like. To this end, the photolithography process through the third annealing must be performed on the selected substrate using the available the photolithography equipment. This delays the production time, namely delays the photolithography process of the next lot. Accordingly, the overall productivity of the semiconductor device fabrication process is negatively impacted.
Secondly, some defects that can only be uncovered after the fourth annealing are due to minor discrepancies in the chemical composition of the photoresist or due to foreign material introduced from raw material used in the fabrication process or as a result of the transportation of the substrates through the semiconductor device fabrication equipment. In these case, the after flow inspection reveals the presence of such defects. Thus, the after develop inspection must be performed to recognize the exact cause of the defects. Also, tests must be performed to determine and modify the temperature or time of the fourth annealing. Such extensive testing is time-consuming and again, decreases the overall productivity that can be achieved in the semiconductor device manufacturing process.